Large displays can be prohibitively expensive as the cost to manufacture display panels rises exponentially with display area. This exponential rise in cost arises from the increased complexity of large monolithic displays, the decrease in yields associated with large displays (a greater number of components must be defect free for large displays), and increased shipping, delivery, and setup costs. Tiling smaller display panels to form larger multi-panel displays can help reduce many of the costs associated with large monolithic displays.
FIG. 1 shows a block diagram illustration of a conventional multi-panel display system 100 that includes display panels 101A-D arranged as multi-panel display 150. The four smaller display panels 101A-D may be conventional flat panel televisions or monitors. The individual images displayed by each display panels 101A-D may constitute a sub-portion of the larger overall-image collectively displayed by multi-panel display 150. Each display panel includes a timing controller (“TCON”) 109 coupled to receive image content from CPU/GPU 103 and coupled to control driver 111 to drive pixel region 115. CPU/GPU 103 reads media 102 and prepares the image content in media 102 to be displayed on multi-panel display 150. Media 102 may be an optical disc or be streaming content received from a remote server.
Tiling smaller display panels 101 to form a multi-panel display can come with additional challenges. When the smaller display panels 101 are high-resolution, the multi-panel display 150 displays a very large overall-image that is even higher resolution (e.g. 5-100 megapixels or more). Updating the high resolution overall-image(s) at a given refresh rate (e.g. 30 frames per second) on multi-panel display 150 can create processing throughput issues for CPU/GPU 103, TCONs 109, and drivers 111 that drive the pixel regions 115 because the hardware uses the conventional raster scanning that updates the entire complement of pixels on multi-panel display 150.
Building hardware to drive higher resolution images at video frame rates onto multi-panel display 150 using raster scanning would likely require power hungry processing hardware that would be relatively expensive. Therefore, when a peak data condition occurs in the driving hardware while processing the image content (e.g. during a scene change), a conventional approach is to reduce the frame rate to allow the driving hardware to catch up. However, the conventional approaches to dealing with a peak data condition are often noticed by viewers of multi-panel display 150 as they see image artifacts in the overall-image displayed by multi-panel display 150. One example of an image artifact that may be seen by viewers during a peak data condition is known as “image shearing,” as the timing or rendering between display panels 101 is out of sync.